The present invention generally relates to a data read circuit for a semiconductor memory, and more particularly to a data read circuit for reading data according to changes of signals at precharge levels.
Referring to FIG. 1, a conventional data read circuit for a DRAM 100 is equipped with a plurality of memory cells C forming a cell array, a plurality of word lines WL, a plurality of bit lines BL, and a sense amplifier (hereafter referred to as a sense amp) 2. Each memory cell C is connected to one of word lines WL and one of a pair of bit lines BL and /BL, respectively.
Each bit line BL, /BL is connected to a bit line BLSA or /BLSA via a transfer gate 1, respectively. The bit lines BLSA, /BLSA are connected to the sense amp 2. The transfer gate 1 includes an N-channel MOS transistor having a gate for receiving a bit line select signal .phi.BT. When the bit line select signal .phi.BT has a High (H) level, the transfer gate 1 is turned on.
The sense amp 2 is connected between the bit lines BLSA and /BLSA and the potential difference between the bit lines BLSA and /BLSA during its activation. The sense amp 2 comprises an inverter circuit including a P-channel MOS transistor Tr1 and an N-channel MOS transistor Tr2 and an inverter circuit including a P-channel MOS transistor Tr3 and an N-channel MOS transistor Tr4. The inverter circuits are connected inversely to each other with respect to the bit lines BLSA and /BLSA. The transistors Tr1 and Tr3 have a source for receiving a supply of an activation power supply signal V.sub.SAH and the transistors Tr2 and Tr4 have a source for receiving a supply of an activation power supply signal V.sub.SAL. When the activation power supply signal V.sub.SAH has a high potential Vcc and the activation power supply signal V.sub.SAL has a low potential Vss, the sense amp 2 is activated. When the activation power supplies V.sub.SAH and V.sub.SAL have the same level, the sense amp 2 is deactivated.
Data buses DB and /DB are connected to the bit lines BLSA and /BLSA via a transfer gate 3, respectively. The transfer gate 3 includes an N-channel MOS transistor having a gate for receiving a column select signal Y.sub.SEL. When the column select signal Y.sub.SEL has an H-level, the transfer gate 3 is turned on.
Each bit line BLSA and /BLSA is connected to a precharge circuit 4. The precharge circuit 4 is connected between the bit line BLSA or /BLSA and a precharge power supply Vcc/2, respectively and an N-channel MOS transistor having a gate for receiving a precharge signal .phi.BR. When the signal .phi.BR has an H-level, the precharge circuit 4 is activated, the precharge power supply having a Vcc/2 level is supplied to the bit lines BLSA and /BLSA, and both of the bit lines BL and /BL are precharged to the Vcc/2 level.
The operation of the data read circuit 100 will now be described with reference to FIG. 2. As shown in FIG. 2, when the bit line select signal .phi.BT is maintained at the H-level, assume that a word line WL1 is selected in the preceding cycle, for example. In this case, the cell data read from the memory cell C that corresponds to the word line WL1 is amplified by the sense amp 2 and output to the bit lines BLSA and /BLSA.
To improve the read and write efficiency of the cell data, the power supply Vcc level is boosted before being supplied to the word line WL1. To improve the transfer efficiency of the transfer gate 1, the power supply Vcc level is boosted and then used as the bit line select signal .phi.BT.
When the word line WL1 falls to the Low (L) level from this boosted state and subsequently both of the activation power supplies V.sub.SAH and V.sub.SAL converge to the Vcc/2 level, the sense amp 2 is deactivated. On the other hand, the precharge signal .phi.BR rises to the H-level and the bit lines BLSA and /BLSA are precharged to the Vcc/2 level.
After the precharge circuit 4 has been deactivated by setting the precharge signal .phi.BR to the L-level in the current cycle, for example, the word line WL2 is selected (the word line WL2 rises to the H-level). In this case, the cell data is read from the selected memory cell C to the bit line /BLSA and a slight potential difference (.alpha.) is generated between the bit lines BLSA and /BLSA based on the cell data.
When the activation power supply signal V.sub.SAH at the Vcc level and the activation power supply signal V.sub.SAL at the Vss level are supplied to the sense amp 2, the sense amp 2 is activated.
Hereupon, the potential difference (.alpha.) between the bit lines BLSA and /BLSA is increased by the operation of the sense amp 2. At this time, the cell data is rewritten to the memory cell C.
Subsequently, when the column select signal Y.sub.SEL is set to the H-level, the two transfer gates 3 are turned on and the cell data amplified by the sense amp 2 is output to the data buses DB and /DB. After the word line WL2 has been selected, the sense amp 2 is deactivated, the precharge circuit 4 is activated, and the bit lines BL, /BL, BLSA, and /BLSA are precharged to the Vcc/2 level.
The single cycle read operation is synchronized with a single cycle control signal /RAS (not illustrated).
Since the bit lines BLSA and /BLSA are precharged to the Vcc/2 level when the sense amp 2 is activated, when the level of one of the bit lines BLSA and /BLSA slightly rises from or falls to the Vcc/2 level, the cell data is read.
Hereupon, even if the voltage Vcc is supplied to the sense amp 2 by the activation power supply signal V.sub.SAH and the voltage Vss is supplied to the sense amp 2 by the activation power supply signal V.sub.SAL, the gate potential and the drain potential of each transistor Tr1 to Tr4 of the sense amp 2 are set in the vicinity of the Vcc/2 level. Hence, the voltage between the source and the drain of each transistor Tr1 to Tr4 is set to Vcc/2.+-..alpha. (.alpha. indicates the potential change component of the bit lines caused by reading the cell data) or Vcc/2. The voltage between the gate and the source of each transistors Tr1 to Tr4 is also set to Vcc/2.+-..alpha. or Vcc/2.
As a result, because the voltage between the source and the drain and the voltage between the gate and the source of each transistor Tr1 to Tr4 are not fully secured for the potential difference of the power supply Vcc and Vss, the current drive performance of each transistor Tr1 to Tr4 is not be fully utilized. The deterioration becomes more pronounced as the voltage of the Vcc power supply decreases resulting in a lower operation speed.
Further, the precharge operation of each bit line BL, /BL, BLSA, /BLSA to the Vcc level and the amplification operation of the potential difference of the bit lines BL, /BL, BLSA, /BLSA based on the operation of the sense amp 2 are performed for each read cycle, respectively.
Accordingly, by the precharge operation and the amplification operation, charging current and discharging current are applied among the bit lines BL, /BL, BLSA, and /BLSA, the precharge circuit 4, and the sense amp 2. The current consumed by these charging and discharging currents accounts for a large proportion of the current consumption of the entire DRAM 100. Therefore, only when the current consumption based on the precharge operation and the amplification operation is reduced, is the power consumption of the DRAM 100 reduced effectively.
On the other hand, with the increase of storage capacity, because the number of memory cells connected to each bit line increases and the length of the bit line also increases, the capacity load and the resistance load for the precharge circuit increase. Hence, because the time required for the precharge circuit and the amplification operation of the bit line potential is prolonged, high-speed data read is difficult to achieve.
Accordingly, it is an object of the present invention to provide a data read circuit for a semiconductor memory with improved reading speed and reduced power consumption.